Flash memory is widely used as a memory for multimedia card since it can hold a memory without supplying an electric power. Recently, it is expected that flash memory with large capacities will be further developed. In order to realize this larger capacity, flash memory needs to be further integrated on a large-scale.
One of the methods of large scale integration of flash memory is disclosed in the Japanese Patent Application No. 2001-118944 and Japanese Patent Application No. 2004-55617. In this method, a silicon layer of floating gates is divided into two layers, which are deposited. First, an initial silicon layer is formed and isolation is then performed. Subsequently, for the formation of a second silicon layer, the second silicon layer is self-aligned and selectively deposited on only the first silicon layer.
The methods disclosed in Japanese Patent Publication No 2001-118944 and Japanese Patent Publication No. 2004-55617 feature that the second silicon layer is laterally expanded and grown on the insulating film for isolation to form the floating gates. These methods allow the floating gate to be wider than a tunnel insulating film and the distance between adjacent floating gates to be less than the minimum feature size. As a result, a large coupling ratio can be realized.
In addition, these methods allow a floating gate end to inevitably have a round structure, thereby crowding of the electric field can be suppressed.
In addition, one of the methods for large scale integration of flash memory is disclosed in the Japanese Patent Publication No. 2001-284556. In this method, after the tunnel gate insulating film is first formed, isolation process is performed. Next, the floating gate is formed.